![]() ![]() Said integrator has at least a first capacitance and a second capacitance, each being implemented by MOS transistors which have drains and sources coupled to a common node and which receive said first and second components by gates, and wherein said comparator comprises at least a first comparator and a second comparator coupled to said first and second capacitance, said first and second comparator receiving said reference signal, and said feedback circuit comprising at least a first feedback unit and a second feedback unit coupled to said first and second capacitances, respectively, wherein said first feedback unit and said second feedback unit each have serially coupled transistors being responsive to digital auxiliary signals from said first comparator and said second comparator, respectively, whereby said digital auxiliary signals return to zero with a clock signal.ΔΆ. ![]() ![]() ![]() A signal processing circuit comprising an analog-to-digital converter for converting a differential analog signal having a first component and a second component using an integrator for integrating said analog signal a comparator for comparing an integrated form of said analog signal to a reference signal to produce a digital signal on an output of said analog-to-digital converter which is related to said analog signal, and a feedback circuit coupled to said output for converting said digital signal to an analog feedback signal for presenting negatively to said integrator, wherein ![]()
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